H2M: Heuristics for Heterogeneous Memory

H2M is a ANR-DFG project between the TADaaM team at Inria Bordeaux–Sud-Ouest (France) and the HPC Group at RWTH Aachen University (Germany) from 2021 to 2023.
The overall goal is to leverage hwloc's knowledge of heterogeneous memory up to programming languages such as OpenMP to ease the allocations of data sets in the appropriate target memories.

News

2023/03/29-31: Face-to-face meeting at Inria Bordeaux.

2022/10/19-21: Face-to-face meeting in the Zuse-Institute in Berlin.

2022/06-08: J. Klinkenberg visited Inria Bordeaux for 3 months as part of the H2M project.

2022/03/15-17: Face-to-face meeting in Aachen, where we visited the aixCAVE.

2021/11/18-19: First in-person meeting (finally!) in Paris.

2021/01/29: The project kick-off meeting was held in videoconference.

Members

Inria

Brice Goglin (French coordinator)
Emmanuel Jeannot
Clément Foyer until 2022/08, now at University of Reims
Andrès Rubio Proaño until 2021/10, now at RIKEN.

RWTH Aachen University

Christian Terboven (German coordinator)
Jannis Klinkenberg

Anara Kozhokanova

Workpackages

WP1: Quantifying Heterogeneous Memory.

Task 1.1: Review of heterogeneous memory architecture trends.
Task 1.2: Identifying the memory topology in a platform.
Task 1.3: Exposing raw memory characteristics to runtimes.
Task 1.4: Quantification of the influence on application performance.
Task 1.5: Quantification of the influence on application capabilities.

WP2: Abstracting Memory Allocation.

Task 2.1: Memory Allocation with Explicit Data Type Information.
Task 2.2: Specification of Initial Memory Access Pattern.
Task 2.3: Modification of of Memory Access Pattern over Time.

WP3: Runtime Heuristics.

Task 3.1: Thread Placement with respect to Memory Hierarchy.
Task 3.2: Data Placement in Heterogeneous Memory Architectures.
Task 3.3: Data Movement based on Information from Annotated Allocations.

WP4: Defining Concepts to extend Parallel Programming Systems.

Task 4.1: Constructs and APIs to query the memory subsystem.
Task 4.2: Constructs and APIs to annotate memory allocation.
Task 4.3: Constructs and APIs to facilitate data movement.

WP5: Evaluating our Contributions.

Task 5.1: Performance measurements of heterogeneous memory subsystems.
Task 5.2: Implementation of memory allocation abstractions in codes.
Task 5.3: Evaluation of these codes on modern architectures.

Publications

J. Klinkenberg, A. Kozhokanova, C. Terboven, C. Foyer, B. Goglin, and E. Jeannot. H2M: Exploiting Heterogeneous Shared Memory Architectures. In: Future Generation Computer Systems, 148:39-55, November 2023. DOI Online

C. Foyer, B. Goglin, and A. Rubio Proaño. A Survey of Software Techniques to Emulate Heterogeneous Memory Systems in High-Performance Computing. In: Parallel Computing, 116:103023, 2023. DOI Online

A. Kozhokanova, B. Wang, C. Terboven, and M. Mueller. Power-aware Computing with Optane Persistent Memory Modules. In: The 32nd Heterogeneity in Computing Workshop (HCW) in conjunction with IPDPS. St. Petersburg, Florida, USA. May 2023.

C. Foyer, B. Goglin, E. Jeannot, J. Klinkenberg, A. Kozhokanova, and C. Terboven. H2M: Towards Heuristics for Heterogeneous Memory. In: Proceedings of the 2022 IEEE Cluster Conference, Heidelberg, Germany, September 2022. Poster. DOI Online

B. Goglin and A. Rubio Proaño. Using Performance Attributes for Managing Heterogeneous Memory in HPC Applications. In: The 23rd IEEE International Workshop on Parallel and Distributed Scientific and Engineering Computing (PDSEC 2022), held in conjunction with IPDPS 2022, Lyon, France, May 2022. DOI Online

C. Foyer and B. Goglin. Using Bandwidth Throttling to Quantify Application Sensitivity to Heterogeneous Memory, In: Workshop on Memory Centric High Performance Computing, MCHPC'21, St. Louis, MO, USA, November 2021. IEEE. DOI Online

References

J. Klinkenberg, P. Samfass, M. Bader, C. Terboven and M. S. Müller. Reactive Task Migration for Hybrid MPI+OpenMP Applications, In: Parallel Processing and Applied Mathematics (PPAM 2019), Springer International Publishing, pp. 59–71. DOI

N. Denoyelle, B. Goglin, A. Ilic, E. Jeannot, and L. Sousa. Modeling Non-Uniform Memory Access on Large Compute Nodes with the Cache-Aware Roofline Model. In: IEEE Transactions on Parallel and Distributed Systems 30.6 (June 2019), pp. 1374–1389. DOI Online

J. Sewall, S. J. Pennycook, A. Duran, C. Terboven, X. Tian, and R. Narayanaswamy. Developments in memory management in OpenMP. In: IJHPCN 13.1 (2019), pp. 70–85. DOI

E. A. León, B. Goglin, and A. R. Proaño. M&MMs: Navigating Complex Memory Spaces with hwloc. In: The Fifth International Symposium on Memory Systems Proceedings (MEMSYS19). Washington, DC: ACM, Oct. 2019, pp. 149–155. DOI Online

E. Jeannot, G. Mercier, and F. Tessier. Process Placement in Multicore Clusters: Algorithmic Issues and Practical Techniques. In: IEEE Transactions on Parallel and Distributed Systems 25.4 (Apr. 2014), pp. 993–1002. DOI Online

A. E. Eichenberger, C. Terboven, M. Wong, and D. an Mey. The Design of OpenMP Thread Affinity. In: OpenMP in a Heterogeneous World - 8th International Workshop on OpenMP, IWOMP 2012,Rome, Italy, June 11-13, 2012. Proceedings. Ed. by B. M. Chapman, F. Massaioli, M. S. Müller, and M. Rorro. Vol. 7312. Lecture Notes in Computer Science. Springer, 2012, pp. 15–28. DOI.

Acknowledgments

This research is funded by the following grants: